ライフサイエンスコーパス: wafer

1 s were utilized, a glass slide and a silicon wafer.

2 own on semiconducting single crystal silicon wafer.

3 id molecules from a fingerprint on a silicon wafer.

4 nogaps in a metal film over an entire 4-inch wafer.

5 rs) properties is fabricated on a 6" silicon wafer.

6 than measured on a single crystal reference wafer.

7 A, and pack 150,000 such devices on a 4-inch wafer.

8 etched arrays of pyramidal pits in a silicon wafer.

9 ble fabrication of microcolumns in a silicon wafer.

10 arrange a 3 m long column on a 4 in. silicon wafer.

11 ake multiple battery devices out of a single wafer.

12 of silicon nanowires generated on a silicon wafer.

13 cally integrated on a single silicon carbide wafer.

14 can be much larger than those of the growth wafer.

15 were fabricated on a standard 4-in. silicon wafer.

16 e applying a voltage bias across the silicon wafer.

17 olarization of neurons cultured on a silicon wafer.

18 ly 40 columns could be fabricated on a 4-in. wafer.

19 es to the silicon oxide surface of a silicon wafer.

20 cal stability as an oxide grown on a silicon wafer.

21 ectors, and bipolar transistors, on the same wafer.

22 as to have crack-free and low-bow (<50 mum) wafer.

23 nm nanowires distant by 28 nm across 6-inch wafer.

24 um is based on a five-core heterogeneous QCL wafer.

25 he growth of random SWNT networks on silicon wafers.

26 l rigid substrates such as glass and silicon wafers.

27 n microreactor chips fabricated from silicon wafers.

28 ype I collagen and on demineralized collagen wafers.

29 ional systems built on brittle semiconductor wafers.

30 d semiconductors, dielectrics and large-area wafers.

31 h comparable feature sizes formed on silicon wafers.

32 surface-energy gradients on oxidized silicon wafers.

33 s) can be readily mass-produced from silicon wafers.

34 reactive ion etching of silicon-on-insulator wafers.

35 fter surgical implantation of the carmustine wafers.

36 ed to engineer microstructured silicon metal wafers.

37 Ox1 and H2 O2 (aq) as Ox2 with Si powder and wafers.

38 erved in electrochemical measurements on MCT wafers.

39 on is lost as kerf during slicing to produce wafers.

40 d for cadmium zinc telluride (CdZnTe or CZT) wafers.

41 Silicon wafers ([100], single-side polished) coated with 1 micro

42 ating an oxygen activity gradient across the wafer, a continuous valence state library is established

43 und that, with a Si(100)-hydrogen terminated wafer, a Si-ethoxy (Si-OC2H5) surface intermediate forms

44 2 NPA is synthesized in-situ on a 4-inch MHP wafer, able to produce thousands of gas sensing units in

45 zed on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for

46 nd 4.74 nm are achieved, respectively on MCT wafers after CMP.

47 , and asymmetric Ag-Au NPs-decorated silicon wafers (Ag-Au NPs@Si)).

48 evice assembly physically combines a silicon wafer, an elastomer (poly(dimethylsiloxane) (PDMS)), and

49 fully fabricated TFSCs from the original Si wafer and attaching TFSCs to virtually any substrates re

50 ations that exceed the scope of conventional wafer and circuit board technologies due to their unique

51 ator hosts were fabricated on a fused-silica wafer and filled with 3,3'-Diethyloxacarbocyanine iodide

52 tice PC Bragg laser fabricated from the same wafer and find that their performances are comparable.

53 We also used silicon wafer and flexible polyimide-aluminium foil substrates f

54 n wafer, causing it to adhere to the silicon wafer and form a liquid-tight seal around the fibers.

55 o generate ordered nanocavity arrays on a Si wafer and use it in surface-assisted laser desorption/io

56 e fabricated from silicon-on-insulator (SOI) wafers and are fully-depleted with thickness of ~20 nm.

57 ules) on various substrates (such as silicon wafers and glass) by solution-processing is reported.

58 ularly faceted, and they scratch the silicon wafers and increase defect concentrations.

59 f silicon solar microcells created from bulk wafers and integrated in diverse spatial layouts on fore

60 ther these techniques can be scaled to large wafers and non-rigid substrates.

61 e multilayers on planar substrates (e.g., Si wafers and the face of TEPC membranes).

62 films were covalently immobilized on silicon wafers and were treated with protein conjugated on FSNPs

63 ly shaped nozzles micromachined on a silicon wafer, and (3) a spacer which prevents contact between t

64 cm-square silicon chip, covered with a Pyrex wafer, and coated with a dimethyl polysiloxane stationar

65 cm square silicon chip, covered with a Pyrex wafer, and statically coated with dimethyl polysiloxane.

66 ose with intracranially implanted carmustine wafers, and (3) measure the pharmacokinetics of O6-BG an

67 factors, including polymer spheres, silicon wafers, and fibers.

68 -abrasive lapping is used to machine the MCT wafers, and the lapping solution is deionized water.

69 The channels were sealed with a glass wafer anodically bonded to the silicon surface.

70 embled in microwells on a pyrolytic graphite wafer are housed in dual microfluidic chambers.

71 licon nanowires etched from recycled silicon wafers are captured in a polymer matrix that operates as

72 Finally, the polished MCT wafers are cleaned and dried by deionized water and comp

73 cleaved from commercially available silicon wafers are low-cost monolithic monocrystalline materials

74 Secondly, the MCT wafers are polished using the developed CMP slurry.

75 Chemotherapy wafers are the most prominent of the adjuvant treatments

76 plement since it utilizes unmodified silicon wafers as substrates and is extremely insensitive to bot

77 silicon nanocrystals (Cl-SiNCs) and silicon wafers as well as molecular chlorosilanes, were explored

78 les (NPs), obtained via anodic etching of Si wafers, as a basis for undecylenic acid (UDA)- or acryli

79 ed scratching is carried out on silicon (Si) wafers at nanoscale depths of cut to investigate the fun

80 raphene layers on hBN flakes and on sapphire wafers at substrate growth temperatures of 1400 degrees

81 he inherently 2D nature of most conventional wafer-based fabrication methods.

82 The wafer-based first-generation photovoltaic devices have b

83 ed light and multiple reflections within the wafer-based IRE.

84 for the further development of low-cost, Si wafer-based IREs for electrochemical ATR-SEIRAS applicat

85 ace recombination and Auger recombination in wafer-based nanostructured silicon solar cells.

86 A variety of wafer-based processing approaches have been developed to

87 rend in increasing the cost-effectiveness of wafer-based solar cells.

88 electrical properties of conventional, rigid wafer-based technologies but with the ability to be stre

89 are impossible to satisfy with conventional wafer-based technologies or even with those that offer s

90 Unlike traditional wafer-based technologies, laminating such devices onto t

91 jected onto the rim of the TiO2-coated glass wafer, before the entire wafer is exposed to UV irradiat

92 light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent

93 tion advanced lithography or well-controlled wafer bonding techniques to define their critical dimens

94 g compared to the pulsed laser deposition or wafer bonding used in the fabrication of NRPS devices.

95 CdTe by constructing grain boundaries using wafer bonding.

96 ushes were grown from the surface of silicon wafers by atom-transfer radical polymerization.

97 These results demonstrate how virgin NPSi wafer can serve as Cu(2+) sensor.

98 cal etching of highly B-doped p-type silicon wafers can be prepared with tubular pores imbedded in a

99 ints imposed by the supporting semiconductor wafers can enable alternative uses in areas such as biom

100 , we demonstrate that NiPd-NG-Si (Si=silicon wafer) can function as a catalyst and show maximum NiPd

101 manually pressed onto a hydrophobic silicon wafer, causing it to adhere to the silicon wafer and for

102 achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

103 (EDTA) in DMSO exerts superior control over wafer coverage and film thickness, and the results demon

104 Here we demonstrate that a piece of silicon wafer cut by a dicing machine or cleaved manually can be

105 Thin, micromachined Si wafers, designed as internal reflection elements (IREs)

106 We find that these layers organize from the wafer edge as propagating wavefronts having well defined

107 oresis chip has been fabricated into a glass wafer etched with 20-microm-deep channels.

108 osts, on a single 3" x 5" polycarbonate (PC) wafer fabricated by hot embossing.

109 Samples collected at two silicon wafer fabrication facilities ranged from 10.0 to 9120 pp

110 n) and easy to automate, and the low cost of wafer fabrication makes it appropriate for single-use ap

111 The Si-tip wafers feature a rectangular array of nanometer sized Si

112 ilms on a lithographically patterned silicon wafer, followed by complete removal of the silicon subst

113 epoxy are discussed to preserve the silicon wafer for future use.

114 ring the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips a

115 iameter of 2.1+/-0.4 nm deposited onto n-InP wafers form Schottky contacts whose barrier height can b

116 materials are required, these include, e.g., wafers from semiconductor industry or studies on space w

117 In addition to showing full wafer gallium arsenide thin film transfer onto both rigi

118 nanoparticles (H-SiNPs), and planar Si(111) wafers (H-Si(111)), we demonstrate that among different

119 al germanium (Ge) thin films on silicon (Si) wafers has been achieved over large areas with aqueous f

120 of semi-insulating Fe-doped InP crystalline wafers in the 2-700 cm(-1) (0.06-21 THz) spectral region

121 The use of a crystal (the Si wafer) in a disposable manner enables simultaneous prepa

122 he passivating process during the CMP of CZT wafers, indicating by the lowest passivation current den

123 tion enhancement with the benefit of thinner wafer induced open circuit voltage increase.

124 he organic (silane layer)-inorganic (silicon wafer) interface.

125 The 500 mum thick wafer IREs with groove angles of 35 degrees are signific

126 es on demineralized and deproteinized dentin wafer is a powerful tool to determine the functional rol

127 rived from an anisotropically etched silicon wafer is discussed.

128 e TiO2-coated glass wafer, before the entire wafer is exposed to UV irradiation.

129 Raman maps show that the 2'' wafer is relaxed and uniform.

130 ctrodes is fabricated on a monolithic quartz wafer, is a very attractive approach for miniaturization

131 non-birefringent thermal oxide on a silicon wafer; it was followed by lithographic fabrication of a

132 e surface mount chip components, such as the wafer level chip scale packages, chip resistors, and lig

133 rected assembly efficiency of SWNTs toward a wafer level SWNT deposition, Si or SiO(2) substrate was

134 represents a versatile approach for in-situ wafer-level fabrication of high-performance micro/nano g

135 We present here a strategy of in-situ wafer-level fabrication of the high-performance micro/na

136 A batch fabrication process at the wafer-level integrating ring microelectrodes into atomic

137 The microsystem fabrication on a wafer-level is based on a polyimide substrate and includ

138 By introducing colloidal crystal template, a wafer-level ordered homogenous SnO2 NPA is synthesized i

139 ference rejection scheme are integrated on a wafer-level.

140 the analysis are co-entrapped on paper in a "wafer"-like bilayer film of polyelectrolytes (Poly (ally

141 clude liposomal and polymeric nanoparticles, wafers, microchips, microparticle-based nanoplatforms an

142 protocol details a method of fabricating off-wafer, multilayered, asymmetric microparticles from the

143 de (Si3N4)/silicon oxide on a p-type silicon wafer, namely electrolyte-oxide-nitride-oxide-Si (EONOS)

144 The scratching is conducted on a Si wafer of 150 mm diameter with an ultraprecision grinder

145 as grown on copper film and transferred to a wafer of diamond-like carbon.

146 to investigate the fundamental mechanisms in wafering of solar cells.

147 ble films were transferred to single-crystal wafers of at least 200 mm in diameter, flexible plastics

148 s of glass, near-infrared imaging devices on wafers of silicon, and photovoltaic modules on sheets of

149 However, growing large, high quality wafers of these materials, and intimately integrating th

150 synthesized high-quality single-crystalline wafers of Tl(6)SeI(4) with detector-grade resistivities

151 ble conducting nanostructures directly on Si wafers opens new opportunities to incorporate ultrahigh-

152 ursor, o-B(10)C(2)H(12), confined between Si wafer or NaCl plates gives microcrystalline deposits of

153 eve with technologies that use semiconductor wafers or glass plates as substrates.

154 By HVPE method, overgrowth of thick GaN wafer over 200 mum has been achieved free of residual st

155 sample was a nearly intrinsic n-type Si(100) wafer patterned with 2-micrometer-wide stripes of highly

156 ation directly on conventional semiconductor wafer platforms and, therefore, promises to allow the in

157 edestal sensor array fabricated over through-wafer pores compatible with vertical flow fields to incr

158 Methods of surface treatment of the wafer prior to casting and PDMS casting of the epoxy are

159 nd this behavior is observed across multiple wafers produced in different growth chambers.

160 nd systems based upon single-crystal silicon wafers provide convenient, straightforward purification.

161 of photolithography and requires no silicon wafer, replica molding, and plasma bonding like microflu

162 The microdevice consists of a four-wafer sandwich combining glass CE separation channels, m

163 The quartz crystal is an AT-cut wafer sandwiched between two neoprene O-rings within the

164 diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal a

165 Wafer scale (cm(2)) arrays and networks of nanochannels

166 o tri-gate transistors and photodetectors at wafer scale (cm(2)) without postgrowth transfer or align

167 h provides bifunctional scanning probes at a wafer scale and at low cost.

168 facile and reproducible method of producing wafer scale atomically thin MoS2 layers has been develop

169 pes and tunable compositions are realized on wafer scale for metallic glasses including the marginal

170 mensional (2D) MoS2 have been fabricated and wafer scale growth of 2D MoS2 has been realized, the fun

171 tercalation method, which is compatible with wafer scale growth of heterostructures.

172 We use electron beam lithography and wafer scale processes to create silicon nanoscale pillar

173 The realization of the wafer scale production of single crystalline graphene fi

174 to fabricate well-ordered patterns over the wafer scale with feature sizes below the resolution of c

175 rystalline VO2 thin films have been grown on wafer scale, exhibiting more than four orders of magnitu

176 et up to be manufacturable and testable on a wafer scale, requiring no cleaved facets or special mirr

177 on of homogenous few layer MoS2 films at the wafer scale, resulting from the novel chelant-in-solutio

178 sistors can be efficiently fabricated on the wafer scale.

179 ingle-digit nanometre dimensions over 200 mm wafer scale.

180 nanoparticle arrays can be manufactured over wafer-scale areas on a variety of substrates.

181 -up and top-down fabrication techniques over wafer-scale areas.

182 Photolithography is used to generate a wafer-scale array of microwells in a layer of photoresis

183 the electrochemical synthesis of large-area, wafer-scale arrays of rough Si nanowires that are 20-300

184 these films we successfully demonstrate the wafer-scale batch fabrication of high-performance monola

185 icroIDE) electrode-arrays were fabricated on wafer-scale by combining nanoimprint and photolithograph

186 Hybrid glass-polydimethylsiloxane (PDMS) wafer-scale construction is used to combine 250-nl react

187 ique will lead the field toward synthesis of wafer-scale crystalline perovskites, necessary for the f

188 Wafer-scale deposition of mono to few layer TMD films ha

189 stals have been demonstrated; however, their wafer-scale deposition remains a challenge.

190 Toward wafer-scale epitaxial and grain boundary-free film is gr

191 We have demonstrated a low-temperature wafer-scale etching and thin film deposition method for

192 Wafer-scale fabrication of complex nanofluidic systems w

193 These findings are promising towards wafer-scale fabrication of graphene photodetectors appro

194 Here, we demonstrate the wafer-scale fabrication of highly reflective and conduct

195 In this way, the foundry-based wafer-scale fabrication technology for silicon photonics

196 angle color reflection, and is applicable to wafer-scale fabrication using conventional thin film tec

197 The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels

198 port the preparation of high-mobility 4-inch wafer-scale films of monolayer molybdenum disulphide (Mo

199 A wafer-scale graphene circuit was demonstrated in which a

200 , which are formed by depositing alternating wafer-scale graphene sheets and thin insulating layers,

201 bstrates (Ni(C)/(B, N)-source/Ni) in vacuum, wafer-scale graphene/h-BN films can be directly formed o

202 realization in commercial devices demands a wafer-scale growth approach for high-quality transition

203 Wafer-scale heterostructures consisting of single-layer/

204 ser scribing fabrication method to integrate wafer-scale high-performance graphene-based in-plane tra

205 n this work, we propose a novel approach for wafer-scale integration of 2D materials on CMOS photonic

206 the laser scribed graphene could be used for wafer-scale integration of a variety of graphene-based e

207 The approach uses wafer-scale optoelectronics formed in unusual, two-dimen

208 This DNA nanolithography enables wafer-scale patterning of two-dimensional electronic mat

209 We developed OECT devices in a wafer-scale process and used them as electrophysiologica

210 We describe a wafer-scale process for manufacturing strongly adhering

211 method offers great commercial potential for wafer-scale processes.

212 tion techniques is an exciting route towards wafer-scale quantum technologies.

213 However, its use is generally restricted to wafer-scale samples or specific micro-magnetic devices,

214 Here we report the generation of wafer-scale semiconductor films with a very high level o

215 Wafer-scale single-crystalline graphene monolayers are h

216 ay also prove effective for the synthesis of wafer-scale single-crystalline monolayers of other two-d

217 t photovoltaics use high-purity, large-area, wafer-scale single-crystalline semiconductors grown by s

218 a technique for depositing and patterning of wafer-scale two-dimensional metal chalcogenide compounds

219 n film depositions, and is of unprecedented (wafer-scale) extent.

220 andom nanostructures in amorphous silicon at wafer scales that achieved over 160% light absorption en

221 inally, we show that compacting HKUST-1 into wafer shapes partially collapses the framework, decreasi

222 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit compl

223 gold-capped nanopillars, which showed an in-wafer signal variation of only 11.7%.

224 dvantage of our fabrication method, a 6 inch wafer size heterogeneous surface was prepared.

225 t the same time inherently restricted by the wafer size, its planar geometry and the complexity assoc

226 xpensive procedure for epitaxial lift-off of wafer-size flexible and transparent foils of single-crys

227 Wafer-sized single-crystalline Cu (100) surface can be r

228 thylene glycol based cutting fluid during Si wafer slicing in semiconductor fabrication.

229 rated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materi

230 t-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the co

231 ode consisting of unpolymerized holes in the wafer structure of the microparticle; this code serves t

232 sphorus nanowires (>1 mm) selectively onto a wafer substrate from red phosphorus powder and a thin fi

233 low, micrometer-sized wells etched into a Si wafer substrate so that the bilayers are near (within hu

234 ur deposition method is scalable to a 100 mm wafer substrate, with around 50% of the wafer surface co

235 depth profile for an organic overlayer on a wafer substrate.

236 peratures we observe etching of the sapphire wafer surface by the flux from the atomic carbon source,

237 0 mm wafer substrate, with around 50% of the wafer surface covered by aligned crystals.

238 molecular weights and compositions across a wafer surface, with complex geometries and diverse featu

239 s of nanometers) but not in contact with the wafer surface.

240 s uniformly transferred onto 2" GaN or 4" Si wafer surfaces as a release buffer layer.

241 nge crystalline order over arbitrarily large wafer surfaces.

242 his approach relies on processing a separate wafer that is then mechanically mounted on the 2DEG mate

243 nfirms that, for Irganox 1010 deposited on a wafer, the depth resolution at the Irganox 1010/substrat

244 When performed on a mesoporous Si wafer, the perfluoro reagent yields a superhydrophobic s

245 rier concentrations across a half-centimetre wafer, these results boost the prospects of using epitax

246 Reducing the silicon wafer thickness at a minimized efficiency loss represent

247 erly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only arou

248 thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency

249 The sensor was fabricated on a silicon wafer through photolithography to define the sensor geom

250 ea formats, in a manner that also allows the wafer to be reused for additional growths.

251 ucted the thermal chip using SU-8 on a glass wafer to minimize the heat loss.

252 ing formed by thermal oxidation of a silicon wafer to remove destructive interference of the reflecte

253 with high yield and fidelity from a SiO2/Si wafer to various non-Si based substrates, including pape

254 rication of the micropatterned silicon metal wafers to casting of silicone molds, microfluidic patter

255 surfaces of commercially available sapphire wafers to guide the self-assembly of block copolymer mic

256 -doped CdTe using high-purity single crystal wafers to investigate the mechanisms that limit p-type d

257 weeks) by intermittent feeding of medicated wafers to model chronic and relapsing disease.

258 We used photolithography on silicon wafers to synthesize microarrays (Intel arrays) that con

259 delivery systems such as microparticles and wafers used as controlled drug release depots, to multif

260 was first deposited on a low-resistivity Si wafer using a convective self-assembly method.

261 ividual carbon nanotubes (CNTs) on a silicon wafer using a conventional optical microscope.

262 trochemical etch of a single-crystal silicon wafer using a programmed current-time waveform.

263 rotrap array etched from a silica-on-silicon wafer using conventional semiconductor fabrication techn

264 ese chips were batch-fabricated on a silicon wafer using photolithographic processes and with Parylen

265 Polymer 1 was cross-linked onto silicon wafers using an electron beam writer forming micro- and

266 First, we modified polycarbonate wafers using an electrophilic aromatic substitution reac

267 osensors were fabricated on oxidized silicon wafers using chemical vapor deposition grown carbon nano

268 lide, 330,000 peptides per assay) on silicon wafers using equipment common to semiconductor manufactu

269 r-water interface and transferred to silicon wafers using Langmuir-Schaefer deposition.

270 cks of 32 x 32 nanowire arrays across 6-inch wafer, using electron beam lithography at 100 kV and pol

271 rs of different compositions, on the same Si wafer, using only a single deposition process and a sing

272 diamond films grown on surface-passivated Si wafers via chemical vapor deposition (CVD) and microstru

273 A glass wafer was etched to create an array of 1-nL wells.

274 devices with four-color emission on the same wafer were demonstrated.

275 Wafers were bonded anodically using an intermediate amor

276 These wafers were fabricated by complementary metal-oxide-semi

277 When low-resistivity silicon wafers were irradiated in air, sulfur hexafluoride, or w

278 polystyrene (PS) films supported on silicon wafers were obtained at temperatures ranging from room t

279 more complicated objects (computer chips and wafers) were obtained.

280 patterning photoresist structures on silicon wafers, which are then used to mold features in elastome

281 cating the removing of oxidized films on MCT wafers, which is difficult to achieve using single H2O2

282 or is fabricated from a silicon-on-insulator wafer with a deliberate curvature to form an arch shape.

283 ime in commonplace commercial n-type silicon wafer with a P dopant density of (1.4+/-0.1) x10(15) cm(

284 ative surface functionalization of a silicon wafer with carboxylated alkyltrichlorosilane has been de

285 Here, a silicon wafer with deep, nanoscale patterns of surface relief se

286 For this purpose, we coated a round glass wafer with photocatalytically active anatase-phase TiO2

287 Metallic Nd was deposited onto Si wafers with 0.5, 1, 3, and 6 nm thickness and covered by

288 s obtained uniformly on the whole surface of wafers with a controlled number of graphene layers.

289 Black silicon (bSi) wafers with a high density of high-aspect ratio nanopill

290 other Bacillus species by incubation on bSi wafers with and without nanopillars.

291 transferred to polished silicon or germanium wafers with electrostatically assisted high-speed centri

292 We found that the bSi wafers with nanopillars were indeed very effective in ru

293 However, bSi wafers with or without nanopillars gave no killing or ru

294 lane molecules on naturally oxidized silicon wafers with reference-free total reflection X-ray fluore

295 -PT epitaxial thin films on vicinal (001) Si wafers with the use of an epitaxial (001) SrTiO(3) templ

296 ed graphene was studied by patterning the EG wafers with two geometrically identical macroscopic chan

297 mesoporous TiO2 films, dip-coated on silicon wafer, with controlled porosity in the range of 15 to 50

298 veral areas of SiGe-on-insulator on a single wafer, with the ability to tune the composition of each

299 d killing the growing bacterial cells, while wafers without nanopillars had no bactericidal effect.

300 red with intracranially implanted carmustine wafers, without added toxicity.